Semiconductor chips are used in many applications, including as processor chips for computers, and as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
One general method for making semiconductor chips is referred to as the "bulk" CMOS method, wherein well implants are formed in a bulk silicon substrate to promote subsequent proper functioning of the chip, and then transistor stacks are formed on the substrate. A newer chip making method referred to as "silicon on insulator" or "SOI" has also been introduced which does not require the formation of wells in the substrate, and which provides for faster transistor switching speed, improved resistance to soft error and latch-up, and higher transistor density. Moreover, SOI chips advantageously consume less power when inactive compared to bulk CMOS chips.
As recognized by the present invention, however, the SOI process implicates complications, including the implantation of high doses of oxygen into the substrate. As understood herein, the high dose of oxygen that is required can lead to a relatively high defect rate in the SOI film, consequently requiring high temperature annealing for prolonged periods to alleviate the defects. Unfortunately, this in turn makes it difficult to precisely control the SOI film thickness, which is undesirable because a uniform SOI film thickness promotes optimal chip functioning. Also, because of the prolonged annealing, manufacturing throughput is lower than might be desired. Fortunately, the present invention has recognized the above problems and has provided the solutions herein.